Virtually all complex integrated circuits are designed with the use of computer aided design (CAD) tools. Some CAD tools, called simulators, help the circuit designer verify the operation of a proposed circuit. Logic simulators are CAD tools for circuits that generate binary signals, which either have a value of 0 or 1. Logic simulation is generally much faster and requires much less computer resources than analog circuit simulation because output values for each circuit element are generated by table look-up rather than by computing complex equations.
However, logic simulation has progressively become more complex because of the necessity of taking into account (A) signal delays, (B) signals that are "in transition", and (C) signals having an unknown binary value, such as data values in a datapath circuit, as opposed to the control signals. Furthermore, some large application specific integrated circuits (ASICs) contain so many logic gates that even the most efficient logic simulators require inordinate amounts of computer time or the use of extremely expensive computers in order to perform such simulations in a reasonable amount of time. ASICs being designed at the time of this application can have hundreds of thousands of logic gates, and there will most likely be demand for ASICs with millions of logic gates in the not very distant future.
Current logic simulators do not handle the simulation of such large circuits efficiently. In particular, it has been determined by the inventors of the present invention that most of the computations performed by logic simulators on large circuit simulations are wasted on "useless events" that do not affect the output nodes of the circuit. That is, many signal transitions in such large circuits affect neither (A) the internal stored state of the circuit nor (B) the outputs of the circuit. The prior art event driven logic simulators, however, must simulate all signal transitions because the prior art logic simulators do not have any mechanism for predicting which signal transitions are "useless" and which are "important".
The present invention provides a comprehensive and very simple method of determining which signal transitions have to be simulated and which can be simply ignored. Particularly in large logic circuits having in excess of 1000 logic gates, the present invention has been shown to reduce the number of simulated events by factors ranging from as little as 10 percent to more than 98 percent.